1. Field of the Invention
The present invention relates to a method for preventing aluminum intrusions into a via hole on a semiconductor wafer.
2. Description of the Prior Art
With the increasing complexity of integrated circuits, the surface of the semiconductor wafer cannot provide enough area to form circuit interconnects. In order to form interconnects on this decreasing MOS transistor scale, a multilevel interconnect process is the typical method used in an integrated circuit. In the multilevel interconnects process, a plug is used to electrically connect two conductive layers. Transistors on the wafer connect to each other via the plug so as to form an entire circuit.
Aluminum is usually used as the conductive material in a metallization process because of its good conductive properties, and because it is easy to deposit using a sputtering process. In a typical method for forming a plug, an etching process is performed to form a via hole in a dielectric layer, and a chemical vapor deposition (CVD) process is used to fill tungsten into the via hole so as to form the plug.
Please refer to FIG. 1 to FIG. 3. FIG. 1 to FIG. 3 are schematic diagrams of the prior art method for forming a via plug 30. As shown in FIG. 1, a prior art semiconductor wafer 10 includes a substrate 12, an aluminum layer 14 on the substrate 12, an anti-reflection coating (ARC) 16 on the aluminum layer 14, a dielectric layer 18 on the ARC 16, and a via hole 20 that passes through the dielectric layer 18 and the ARC 16 down to a predetermined depth within the aluminum layer 14. In the prior art method, a thin film deposition process is performed on the semiconductor wafer 10 using a physical vapor deposition (PVD) method. Either a collimator sputtering process, or an ionized metal process, can be used to form a titanium layer 22 on the bottom and on the walls of the via hole 20. Because titanium is good at oxygen gettering, and an ohmic contact at the interface between titanium and silicon can be approached easily at a proper temperature, titanium is usually used in a contact process. However, the titanium layer 22 is limited by the poor step coverage properties of the sputtering process, so the titanium layer 22 that covers the fringe portions of the bottom of the via hole 20 is very thin.
As shown in FIG. 2, the semiconductor wafer 10 is then placed into a chamber that is pre-heated to 400.degree. C. to 450.degree. C. (752.degree. F. to 842.degree. F.). However, aluminum 14 melts and intrudes into the via hole 20 due to the high temperatures of the CVD process. As shown in FIG. 3, a CVD process then forms a titanium nitride layer (TiN) 26 on the surface of the titanium layer 22 and the intrusion aluminum layer 24. The titanium layer 26 is used as a barrier layer to prevent spiking phenomenon at the aluminum/silicon interface, and it also enhances the adhesion of the tungsten. A CVD process is then performed to form a blanket tungsten layer that fills the via hole 20. A tungsten etch back process is performed using a dry etching process to remove the tungsten layer that covers the surface of the dielectric layer 18. The tungsten layer 28 remaining in the via hole 20 forms the via plug 30.
In the prior art method, the chamber is pre-heated before performing the CVD process to deposit the titanium nitride layer 22. The pre-heat temperature helps a subsequent CVD process perform more smoothly. However, the pre-heat temperature is about 400.degree. C. to 450.degree. C. (752.degree. F. to 842.degree. F.), and the melting point of aluminum is lower, about 380.degree. C. (716.degree. F.). Hence, the high temperature of the pre-heat process causes the aluminum to melt and intrude into the via hole 20 from the thin portions of the titanium layer 22. The aluminum layer 24 intruding into the via hole 20 reacts with the titanium layer 22 and forms aluminum titanium (AlTi.sub.3) at the interface. The presence of aluminum titanium results in an increased electrical resistance of the via plug 30, up to 10.OMEGA.to 20.OMEGA.. Furthermore, it can effect the reliability of the circuit.